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80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT
s High-Performance Embedded Architecture -- 25 MIPS Burst Execution at 25 MHz -- 9.4 MIPS* Sustained Execution at 25 MHz s 512-Byte On-Chip Instruction Cache -- Direct Mapped -- Parallel Load/Decode for Uncached Instructions s Multiple Register Sets -- Sixteen Global 32-Bit Registers -- Sixteen Local 32-Bit Registers -- Four Local Register Sets Stored On-Chip -- Register Scoreboarding s 4 Gigabyte, Linear Address Space s Pin Compatible with 80960KA s Built-in Interrupt Controller -- 31 Priority Levels, 256 Vectors -- 3.4 s Latency @ 25 MHz s Easy to Use, High Bandwidth 32-Bit Bus -- 66.7 Mbytes/s Burst -- Up to 16 Bytes Transferred per Burst s 132-Lead Packages: -- Pin Grid Array (PGA) -- Plastic Quad Flat-Pack (PQFP) s On-Chip Floating Point Unit -- Supports IEEE 754 Floating Point Standard -- Four 80-Bit Registers -- 13.6 Million Whetstones/s (Single Precision) at 25 MHz
The 80960KB is a member of Intel's i960(R) 32-bit processor family, which is designed especially for embedded applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in interrupt controller. The 80960KB has a large register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess of 9.4 million instructions per second*. The 80960KB is well-suited for a wide range of applications including nonimpact printers, I/O control and specialty instrumentation.
FOUR 80-BIT FP REGISTERS 80-BIT FPU
SIXTEEN 32-BIT GLOBAL REGISTERS
64- BY 32-BIT LOCAL REGISTER CACHE
32-BIT INSTRUCTION EXECUTION UNIT
INSTRUCTION FETCH UNIT
512-BYTE INSTRUCTION CACHE
INSTRUCTION DECODER
MICROINSTRUCTION SEQUENCER
MICROINSTRUCTION ROM
32-BIT BUS CONTROL LOGIC
32-BIT BURST BUS
Figure 1. The 80960KB Processor's Highly Parallel Architecture * Relative to Digital Equipment Corporation's VAX-11/780 at 1 MIPS (VAX-11TM is a trademark of Digital Equipment Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. May 1993 (c) INTEL CORPORATION, 1993 Order Number: 270565-006
80960KB
1.0
THE i960(R) PROCESSOR
The 80960KB is a member of the 32-bit architecture from Intel known as the i960 processor family. These were especially designed to serve the needs of embedded applications. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and networking. These types of applications require high integration, low power consumption, quick interrupt response times and high performance. Since time to market is critical, embedded microprocessors need to be easy to use in both hardware and software designs.
All members of the i960 processor family share a common core architecture which utilizes RISC technology so that, except for special functions, the family members are object-code compatible. Each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market. Software written for the 80960KB will run without modification on any other member of the 80960 Family. It is also pin-compatible with the 80960KA and the 80960MC which is a military-grade version that supports multitasking, memory management, multiprocessing and fault tolerance.
0000 0000H
FFFF FFFFH
ADDRESS SPACE
ARCHITECTURALLY DEFINED DATA STRUCTURES
FETCH
LOAD
STORE
INSTRUCTION CACHE
INSTRUCTION STREAM
INSTRUCTION EXECUTION
SIXTEEN 32-BIT GLOBAL REGISTERS
g0 g15
PROCESSOR STATE REGISTERS INSTRUCTION POINTER ARITHMETIC CONTROLS PROCESS CONTROLS TRACE CONTROLS
REGISTER CACHE
SIXTEEN 32-BIT LOCAL REGISTERS
r0 r15
FOUR 80-BIT FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 2. 80960KB Programming Environment
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80960KB
1.1.
Key Performance Features
The 80960 architecture is based on the most recent advances in microprocessor technology and is grounded in Intel's long experience in the design and manufacture of embedded microprocessors. Many features contribute to the 80960KB's exceptional performance: 1. Large Register Set. Having a large number of registers reduces the number of times that a processor needs to access memory. Modern compilers can take advantage of this feature to optimize execution speed. For maximum flexibility, the 80960KB provides thirty-two 32-bit registers and four 80-bit floating point registers. (See Figure 2.) 2. Fast Instruction Execution. Simple functions make up the bulk of instructions in most programs so that execution speed can be improved by ensuring that these core instructions are executed as quickly as possible. The most frequently executed instructions such as register-register moves, add/subtract, logical operations and shifts execute in one to two cycles. (Table 1 contains a list of instructions.) 3. Load/Store Architecture. One way to improve execution speed is to reduce the number of times that the processor must access memory to perform an operation. As with other processors based on RISC technology, the 80960KB has a Load/Store architecture. As such, only the LOAD and STORE instructions reference memory; all other instructions operate on registers. This type of architecture simplifies instruction decoding and is used in combination with other techniques to increase parallelism. 4. Simple Instruction Formats. All instructions in the 80960KB are 32 bits long and must be aligned on word boundaries. This alignment makes it possible to eliminate the instruction alignment stage in the pipeline. To simplify the instruction decoder, there are only five instruction formats; each instruction uses only one format. (See Figure 3.)
5. Overlapped Instruction Execution. Load operations allow execution of subsequent instructions to continue before the data has been returned from memory, so that these instructions can overlap the load. The 80960KB manages this process transparently to software through the use of a register scoreboard. Conditional instructions also make use of a scoreboard so that subsequent unrelated instructions may be executed while the conditional instruction is pending. 6. Integer Execution Optimization. When the result of an arithmetic execution is used as an operand in a subsequent calculation, the value is sent immediately to its destination register. Yet at the same time, the value is put on a bypass path to the ALU, thereby saving the time that otherwise would be required to retrieve the value for the next operation. 7. Bandwidth Optimizations. The 80960KB gets optimal use of its memory bus bandwidth because the bus is tuned for use with the on-chip instruction cache: instruction cache line size matches the maximum burst size for instruction fetches. The 80960KB automatically fetches four words in a burst and stores them directly in the cache. Due to the size of the cache and the fact that it is continually filled in anticipation of needed instructions in the program flow, the 80960KB is relatively insensitive to memory wait states. The benefit is that the 80960KB delivers outstanding performance even with a low cost memory system. 8. Cache Bypass. If a cache miss occurs, the processor fetches the needed instruction then sends it on to the instruction decoder at the same time it updates the cache. Thus, no extra time is spent to load and read the cache.
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80960KB
Table 1. 80960KB Instruction Set Data Movement Load Store Move Load Address Arithmetic Add Subtract Multiply Divide Remainder Modulo Shift Logical And Not And And Not Or Exclusive Or Not Or Or Not Exclusive Nor Not Nand Rotate Call/Return Call Call Extended Call System Return Branch and Link Decimal Decimal Move Decimal Add with Carry Decimal Subtract with Carry Bit and Bit Field Set Bit Clear Bit Not Bit Check Bit Alter Bit Scan For Bit Scan Over Bit Extract Modify
Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Debug Modify Trace Controls Mark Force Mark
Branch Unconditional Branch Conditional Branch Compare and Branch
Fault Conditional Fault Synchronize Faults
Miscellaneous Atomic Add Atomic Modify Flush Local Registers Modify Arithmetic Controls Scan Byte for Equal Test Condition Code Modify Process Controls
Floating Point Move Real Add Subtract Multiply Divide Remainder Scale Round Square Root Sine Cosine Tangent Arctangent Log Log Binary Log Natural Exponent Classify Copy Real Extended Compare Conversion Convert Real to Integer Convert Integer to Real
Synchronous Synchronous Load Synchronous Move
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80960KB
Control
Opcode
Displacement
Compare and Branch
Opcode
Reg/Lit
Reg
M
Displacement
Register to Register
Opcode
Reg
Reg/Lit
Modes
Ext'd Op
Reg/Lit
Memory Access-- Short
Opcode
Reg
Base
M
X
Offset
Memory Access-- Long
Opcode
Reg
Base
Mode
Scale
xx
Offset
Displacement
Figure 3. Instruction Formats
1.1.1.
Memory Space And Addressing Modes
1.1.2.
Data Types
The 80960KB offers a linear programming environment so that all programs running on the processor are contained in a single address space. Maximum address space size is 4 Gigabytes (232 bytes). For ease of use the 80960KB has a small number of addressing modes, but includes all those necessary to ensure efficient execution of high-level languages such as C. Table 2 lists the modes. Table 2. Memory Addressing Modes * 12-Bit Offset * 32-Bit Offset * Register-Indirect * Register + 12-Bit Offset * Register + 32-Bit Offset * Register + (Index-Register x Scale-Factor) * Register x Scale Factor + 32-Bit Displacement * Register + (Index-Register x Scale-Factor) + 32-Bit Displacement * Scale-Factor is 1, 2, 4, 8 or 16
The 80960KB recognizes the following data types: Numeric: * 8-, 16-, 32- and 64-bit ordinals * 8-, 16-, 32- and 64-bit integers * 32-, 64- and 80-bit real numbers Non-Numeric: * Bit * Bit Field * Triple Word (96 bits) * Quad-Word (128 bits) 1.1.3. Large Register Set
The 80960KB programming environment includes a large number of registers. In fact, 32 registers are available at any time. The availability of this many registers greatly reduces the number of memory accesses required to perform algorithms, which leads to greater instruction processing speed. There are two types of general-purpose registers: local and global. The 20 global registers consist of sixteen 32-bit registers (G0 though G15) and four
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80960KB 80-bit registers (FP0 through FP3). These registers perform the same function as the general-purpose registers provided in other popular microprocessors. The term global refers to the fact that these registers retain their contents across procedure calls. The local registers, on the other hand, are procedure specific. For each procedure call, the 80960KB allocates 16 local registers (R0 through R15). Each local register is 32 bits wide. Any register can also be used for single or double-precision floating-point operations; the 80-bit floating-point registers are provided for extended precision. 1.1.4. Multiple Register Sets loops and procedure calls that lead to jumping back and forth in the same small section of code. Thus, by maintaining a block of instructions in cache, the number of memory references required to read instructions into the processor is greatly reduced. To load the instruction cache, instructions are fetched in 16-byte blocks; up to four instructions can be fetched at one time. An efficient prefetch algorithm increases the probability that an instruction will already be in the cache when it is needed. Code for small loops often fits entirely within the cache, leading to a great increase in processing speed since further memory references might not be necessary until the program exits the loop. Similarly, when calling short procedures, the code for the calling procedure is likely to remain in the cache so it will be there on the procedure's return. 1.1.6. Register Scoreboarding
To further increase the efficiency of the register set, multiple sets of local registers are stored on-chip (See Figure 4). This cache holds up to four local register frames, which means that up to three procedure calls can be made without having to access the procedure stack resident in memory. Although programs may have procedure calls nested many calls deep, a program typically oscillates back and forth between only two to three levels. As a result, with four stack frames in the cache, the probability of having a free frame available on the cache when a call is made is very high. In fact, runs of representative C-language programs show that 80% of the calls are handled without needing to access memory. If four or more procedures are active and a new procedure is called, the 80960KB moves the oldest local register set in the stack-frame cache to a procedure stack in memory to make room for a new set of registers. Global register G15 is the frame pointer (FP) to the procedure stack. Global and floating point registers are not exchanged on a procedure call, but retain their contents, making them available to all procedures for fast parameter passing. 1.1.5. Instruction Cache
The instruction decoder is optimized in several ways. One optimization method is the ability to overlap instructions by using register scoreboarding. Register scoreboarding occurs when a LOAD moves a variable from memory into a register. When the instruction initiates, a scoreboard bit on the target register is set. Once the register is loaded, the bit is reset. In between, any reference to the register contents is accompanied by a test of the scoreboard bit to ensure that the load has completed before processing continues. Since the processor does not need to wait for the LOAD to complete, it can execute additional instructions placed between the LOAD and the instruction that uses the register contents, as shown in the following example: ld data_2, r4 ld data_2, r5 Unrelated instruction Unrelated instruction add R4, R5, R6 In essence, the two unrelated instructions between LOAD and ADD are executed "for free" (i.e., take no apparent time to execute) because they are executed while the register is being loaded. Up to three load instructions can be pending at one time with three corresponding scoreboard bits set. By exploiting this feature, system programmers and compiler writers have a useful tool for optimizing execution speed.
To further reduce memory accesses, the 80960KB includes a 512-byte on-chip instruction cache. The instruction cache is based on the concept of locality of reference; most programs are not usually executed in a steady stream but consist of many branches,
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80960KB
ONE OF FOUR LOCAL REGISTER SETS
REGISTER CACHE
LOCAL REGISTER SET
R0
31 Figure 4. Multiple Register Sets Are Stored On-Chip
0
R15
1.1.7.
Floating-Point Arithmetic
Table 3. Sample Floating-Point Execution Times (s) at 25 MHz Function Add Subtract Multiply Divide Square Root Arctangent Exponent Sine Cosine 32-Bit 0.4 0.4 0.7 1.3 3.7 10.1 11.3 15.2 15.2 64-Bit 0.5 0.5 1.3 2.9 3.9 13.1 12.5 16.6 16.6
In the 80960KB, floating-point arithmetic has been made an integral part of the architecture. Having the floating-point unit integrated on-chip provides two advantages. First, it improves the performance of the chip for floating-point applications, since no additional bus overhead is associated with floating-point calculations, thereby leaving more time for other bus operations such as I/O. Second, the cost of using floating-point operations is reduced because a separate coprocessor chip is not required. The 80960KB floating-point (real-number) data types include single-precision (32-bit), double-precision (64-bit) and extended precision (80-bit) floating-point numbers. Any registers may be used to execute floating-point operations. The processor provides hardware support for both mandatory and recommended portions of IEEE Standard 754 for floating-point arithmetic, including all arithmetic, exponential, logarithmic and other transcendental functions. Table 3 shows execution times for some representative instructions. 1.1.8. High Bandwidth Local Bus
the processor and the memory and I/O subsystem interfaces. The processor uses the L-Bus to fetch instructions, manipulate memory and respond to interrupts. L-Bus features include: * 32-bit multiplexed address/data path * Four-word burst capability which allows transfers from 1 to 16 bytes at a time * High bandwidth reads and 66.7 MBytes/s burst (at 25 MHz) writes with
The 80960KB CPU resides on a high-bandwidth address/data bus known as the local bus (L-Bus). The L-Bus provides a direct communication path between
Table 4 defines L-bus signal names and functions; Table 5 defines other component-support signals such as interrupt lines.
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80960KB
1.1.9.
Interrupt Handling
1.1.11. Fault Detection The 80960KB has an automatic mechanism to handle faults. Fault types include floating point, trace and arithmetic faults. When the processor detects a fault, it automatically calls the appropriate fault handling routine and saves the current instruction pointer and necessary state information to make efficient recovery possible. Like interrupt handling routines, fault handling routines are usually written to meet the needs of specific applications and are often included as part of the operating system or kernel. For each of the fault types, there are numerous subtypes that provide specific information about a fault. For example, a floating point fault may have the subtype set to an Overflow or Zero-Divide fault. The fault handler can use this specific information to respond correctly to the fault. 1.1.12. Built-in Testability Upon reset, the 80960KB automatically conducts an exhaustive internal test of its major blocks of logic. Then, before executing its first instruction, it does a zero check sum on the first eight words in memory to ensure that the memory image was programmed correctly. If a problem is discovered at any point during the self-test, the 80960KB asserts its FAILURE pin and will not begin program execution. Self test takes approximately 47,000 cycles to complete. System manufacturers can use the 80960KB's selftest feature during incoming parts inspection. No special diagnostic programs need to be written. The test is both thorough and fast. The self-test capability helps ensure that defective parts are discovered before systems are shipped and, once in the field, the self-test makes it easier to distinguish between problems caused by processor failure and problems resulting from other causes. 1.1.13. CHMOS The 80960KB is fabricated using Intel's CHMOS IV (Complementary High Speed Metal Oxide Semiconductor) process. The 80960KB is currently available in 16, 20 and 25 MHz versions.
The 80960KB can be interrupted in two ways: by the activation of one of four interrupt pins or by sending a message on the processor's data bus. The 80960KB is unusual in that it automatically handles interrupts on a priority basis and can keep track of pending interrupts through its on-chip interrupt controller. Two of the interrupt pins can be configured to provide 8259A-style handshaking for expansion beyond four interrupt lines. 1.1.10. Debug Features The 80960KB has built-in debug capabilities. There are two types of breakpoints and six trace modes. Debug features are controlled by two internal 32-bit registers: the Process-Controls Word and the TraceControls Word. By setting bits in these control words, a software debug monitor can closely control how the processor responds during program execution. The 80960KB provides two hardware breakpoint registers on-chip which, by using a special command, can be set to any value. When the instruction pointer matches either breakpoint register value, the breakpoint handling routine is automatically called. The 80960KB also provides software breakpoints through the use of two instructions: MARK and FMARK. These can be placed at any point in a program and cause the processor to halt execution at that point and call the breakpoint handling routine. The breakpoint mechanism is easy to use and provides a powerful debugging tool. Tracing is available for instructions (single step execution), calls and returns and branching. Each trace type may be enabled separately by a special debug instruction. In each case, the 80960KB executes the instruction first and then calls a trace handling routine (usually part of a software debug monitor). Further program execution is halted until the routine completes, at which time execution resumes at the next instruction. The 80960KB's tracing mechanisms, implemented completely in hardware, greatly simplify the task of software test and debug.
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80960KB
Table 4. 80960KB Pin Description: L-Bus Signals (Sheet 1 of 2) NAME CLK2 TYPE I DESCRIPTION SYSTEM CLOCK provides the fundamental timing for 80960KB systems. It is divided by two inside the 80960KB and four 80-bit registers (FP0 through FP3) to generate the internal processor clock. LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and from memory. During an address (Ta) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, bits 0-31 contain read or write data. These pins float to a high impedance state when not active. Bits 0-1 comprise SIZE during a Ta cycle. SIZE specifies burst transfer size in words. LAD1 0 0 1 1 ALE O T.S. O O.D. O O.D. O O.D. LAD0 0 1 0 1 1 Word 2 Words 3 Words 4 Words
LAD31:0
I/O T.S.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is asserted during a Ta cycle and deasserted before the beginning of the Td state. It is active LOW and floats to a high impedance state during a hold cycle (Th). ADDRESS/DATA STATUS indicates an address state. ADS is asserted every Ta state and deasserted during the following Td state. For a burst transaction, ADS is asserted again every Td state where READY was asserted in the previous cycle. WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read. It is latched on-chip and remains valid during Td cycles. DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the L-Bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment; it is high during Ta and Td cycles for a write. DT/R never changes state when DEN is asserted. READY indicates that data on LAD lines can be sampled or removed. If READY is not asserted during a Td cycle, the Td cycle is extended to the next cycle by inserting a wait state (Tw) and ADS is not asserted in the next cycle. BUS LOCK prevents bus masters from gaining control of the L-Bus during Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert LOCK. At the start of a RMW operation, the processor examines the LOCK pin. If the pin is already asserted, the processor waits until it is not asserted. If the pin is not asserted, the processor asserts LOCK during the Ta cycle of the read transaction. The processor deasserts LOCK in the Ta cycle of the write transaction. During the time LOCK is asserted, a bus agent can perform a normal read or write but not a RMW operation. The processor also asserts LOCK during interrupt-acknowledge transactions. Do not leave LOCK unconnected. It must be pulled high for the processor to function properly.
ADS
W/R DT/R
READY
I
LOCK
I/O O.D.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
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80960KB Table 4. 80960KB Pin Description: L-Bus Signals (Sheet 2 of 2) NAME BE3:0 TYPE O O.D. DESCRIPTION BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are used in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to LAD7:0. The byte enables are provided in advance of data: * Byte enables asserted during Ta specify the bytes of the first data word. * Byte enables asserted during Td specify the bytes of the next data word, if any (the word to be transmitted following the next assertion of READY). Byte enables that occur during Td cycles that precede the last assertion of READY are undefined. Byte enables are latched on-chip and remain constant from one Td cycle to the next when READY is not asserted. For reads, byte enables specify the byte(s) that the processor will actually use. L-Bus agents are required to assert only adjacent byte enables (e.g., asserting just BE0 and BE2 is not permitted) and are required to assert at least one byte enable. Address bits A0 and A1 can be decoded externally from the byte enables. HOLD I HOLD: A request from an external bus master to acquire the bus. When the processor receives HOLD and grants bus control to another master, it floats its threestate bus lines and open-drain control lines, asserts HLDA and enters the Th state. When HOLD deasserts, the processor deasserts HLDA and enters the Ti or Ta state. HOLD ACKNOWLEDGE: Notifies an external bus master that the processor has relinquished control of the bus. CACHE indicates when an access is cacheable during a Ta cycle. It is not asserted during any synchronous access, such as a synchronous load or move instruction used for sending an IAC message. The CACHE signal floats to a high impedance state when the processor is idle.
HLDA CACHE
O T.S. O T.S.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state Table 5. 80960KB Pin Description: Support Signals (Sheet 1 of 2) NAME BADAC TYPE I DESCRIPTION BAD ACCESS, if asserted in the cycle following the one in which the last READY of a transaction is asserted, indicates that an unrecoverable error has occurred on the current bus transaction or that a synchronous load/store instruction has not been acknowledged. During system reset the BADAC signal is interpreted differently. If the signal is high, it indicates that this processor will perform system initialization. If it is low, another processor in the system will perform system initialization instead. RESET clears the processor's internal logic and causes it to reinitialize. During RESET assertion, the input pins are ignored (except for BADAC and IAC/INT0), the three-state output pins are placed in a high impedance state and other output pins are placed in their non-asserted states. RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. The HIGH to LOW transition of RESET should occur after the rising edge of both CLK2 and the external bus clock and before the next rising edge of CLK2.
RESET
I
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
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80960KB Table 5. 80960KB Pin Description: Support Signals (Sheet 2 of 2) NAME FAILURE TYPE O O.D. DESCRIPTION INITIALIZATION FAILURE indicates that the processor did not initialize correctly. After RESET deasserts and before the first bus transaction begins, FAILURE asserts while the processor performs a self-test. If the self-test completes successfully, then FAILURE deasserts. The processor then performs a zero checksum on the first eight words of memory. If it fails, FAILURE asserts for a second time and remains asserted. If it passes, system initialization continues and FAILURE remains deasserted. INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC message or an interrupt is pending. The bus interrupt control register determines how the signal is interpreted. To signal an interrupt or IAC request in a synchronous system, this pin -- as well as the other interrupt pins -- must be enabled by being deasserted for at least one bus cycle and then asserted for at least one additional bus cycle. In an asynchronous system the pin must remain deasserted for at least two bus cycles and then asserted for at least two more bus cycles. During system reset, this signal must be in the logic high condition to enable normal processor operation. The logic low condition is reserved. INTERRUPT 1, like INT0, provides direct interrupt signaling. INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines how this pin is interpreted. If INT2, it has the same interpretation as the INT0 and INT1 pins. If INTR, it is used to receive an interrupt request from an external interrupt controller. INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register determines how this pin is interpreted. If INT3, it has the same interpretation as the INT0, INT1 and INT2 pins. If INTA, it is used as an output to control interruptacknowledge transactions. The INTA output is latched on-chip and remains valid during Td cycles; as an output, it is open-drain. NOT CONNECTED indicates pins should not be connected. Never connect any pin marked N.C. as these pins may be reserved for factory use.
IAC/INT0
I
INT1 INT2/INTR
I I
INT3/INTA
I/O O.D.
N.C.
N/A
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
2.0 2.1.
ELECTRICAL SPECIFICATIONS Power and Grounding
board, all Vcc pins must be strapped closely together, preferably on a power plane; all Vss pins should be strapped together, preferably on a ground plane.
The 80960KB is implemented in CHMOS IV technology and therefore has modest power requirements. Its high clock frequency and numerous output buffers (address/data, control, error and arbitration signals) can cause power surges as multiple output buffers simultaneously drive new signal levels. For clean on-chip power distribution, VCC and VSS pins separately feed the device's functional units. Power and ground connections must be made to all 80960KB power and ground pins. On the circuit
2.2.
Decoupling Recommendations
Place a liberal amount of decoupling capacitance near the 80960KB. When driving the L-bus the processor can cause transient power surges, particularly when connected to a large capacitive load.
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80960KB Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance is reduced by shortening board traces between the processor and decoupling capacitors as much as possible.
VCC OPEN-DRAIN OUTPUT 180
2.3.
Connection Recommendations
High Drive Network: VOH = 3.4 V I OL = 25.3 mA 390
For reliable operation, always connect unused inputs to an appropriate signal level. In particular, if one or more interrupt lines are not used, they should be pulled up. No inputs should ever be left floating. All open-drain outputs require a pullup device. While in most cases a simple pullup resistor is adequate, a network of pullup and pulldown resistors biased to a valid VIH (>3.0 V) and terminated in the characteristic impedance of the circuit board is recommended to limit noise and AC power consumption. Figure 5 and Figure 6 show recommended values for the resistor network for low and high current drive, assuming a characteristic impedance of 100 . Terminating output signals in this fashion limits signal swing and reduces AC power consumption. NOTE: Do not connect external logic to pins marked N.C.
VCC OPEN-DRAIN OUTPUT 220
Figure 6. Connection Recommendations for High Current Drive Network
2.4.
Characteristic Curves
Figure 7 shows typical supply current requirements over the operating temperature range of the processor at supply voltage (VCC) of 5 V. Figure 8 and Figure 9 show the typical power supply current (ICC) that the 80960KB requires at various operating frequencies when measured at three input voltage (VCC) levels and two temperatures. For a given output current (IOL) the curve in Figure 10 shows the worst case output low voltage (VOL). Figure 11 shows the typical capacitive derating curve for the 80960KB measured from 1.5V on the system clock (CLK) to 1.5V on the falling edge and 1.5V on the rising edge of the L-Bus address/data (LAD) signals.
Low Drive Network: VOH = 3.0 V IOL = 20.7 mA
330
Figure 5. Connection Recommendations for Low Current Drive Network
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80960KB
VCC = 5.0 V
380 360 340
POWER SUPPLY CURRENT (mA)
320 300 280 260 240 220 200 -60 -40 -20 0 20 40 60 80 100 120 140
25 MHz 20 MHz 16 MHz
CASE TEMPERATURE (C)
Figure 7. Typical Supply Current vs. Case Temperature
TEMP = +22C
400 380
@5.5V 360 @5.0V @4.5V TYPICAL SUPPLY CURRENT (mA) 340 320 300 280 260 240 220 200 180
16
20
25
OPERATING FREQUENCY (MHz)
Figure 8. Typical Current vs. Frequency (Room Temp)
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80960KB
TEMP = +22C
380 360
@5.5V 340 @5.0V @4.5V TYPICAL SUPPLY CURRENT (mA) 320 300 280 260 240 220 200 180 160
16
20
25
OPERATING FREQUENCY (MHz)
Figure 9. Typical Current vs. Frequency (Hot Temp)
(TEMP = +85C, VCC = 4.5V) OUTPUT LOW VOLTAGE (V)
(TEMP = +85C, VCC = 4.5V) 30
FALLING
0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 OUTPUT LOW CURRENT(mA)
THREE-STATE OUTPUT VALID DELAY(ns)
25 20 15 10 5 0 0 20 40 60 80 100 CAPACITIVE LOAD(pF)
RISING
Figure 10. Worst-Case Voltage vs. Output Current on Open-Drain Pins
Figure 11. Capacitive Derating Curve
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2.5.
Test Load Circuit
THREE-STATE OUTPUT
Figure 12 illustrates the load circuit used to test the 80960KB's three-state pins; Figure 13 shows the load circuit used to test the open drain outputs. The open drain test uses an active load circuit in the form of a matched diode bridge. Since the open-drain outputs sink current, only the IOL legs of the bridge are necessary and the IOH legs are not used. When the 80960KB driver under test is turned off, the output pin is pulled up to VREF (i.e., VOH). Diode D1 is turned off and the IOL current source flows through diode D2. When the 80960KB open-drain driver under test is on, diode D 1 is also on and the voltage on the pin being tested drops to VOL. Diode D2 turns off and IOL flows through diode D1.
CL
CL = 50 pF for all signals Figure 12. Test Load Circuit for Three-State Output Pins
IOL OPEN-DRAIN OUTPUT D1 D2
CL
IOL Tested at 25 mA VREF = VCC D1 and D2 are matched
CL = 50 pF for all signals Figure 13. Test Load Circuit for Open-Drain Output Pins
14
80960KB
2.6.
Absolute Maximum Ratings
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Operating Temperature (PGA).............. 0C to +85C Case (PQFP) ......... 0C to +100C Case Storage Temperature ................................. -65C to +150C Voltage on Any Pin................................. -0.5V to VCC +0.5V Power Dissipation .......................................... 2.5W (25 MHz)
2.7.
PGA:
DC Characteristics
80960KB (16 MHz) TCASE = 0C to +85C, VCC = 5V 10% 80960KB (20 and 25 MHz) TCASE = 0C to +85C, VCC = 5V 5% 80960KB (16 MHz) TCASE = 0C to +100C, VCC = 5V 10% 80960KB (20 and 25 MHz) TCASE = 0C to +100C, VCC = 5V 5% Table 6. DC Characteristics
PQFP:
Symbol VIL VIH VCL VCH VOL VOH ICC
Parameter Input Low Voltage Input High Voltage CLK2 Input Low Voltage CLK2 Input High Voltage Output Low Voltage Output High Voltage Power Supply Current: 16 MHz 20 MHz 25 MHz Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Clock Capacitance
Min -0.3 2.0 -0.3 0.55 VCC 2.4
Max +0.8 VCC + 0.3 +0.8 VCC + 0.3 0.45
Units V V V V V V (1,2) (3,4) (5) (5) (5)
Notes
315 360 420 15 15 10 12 10
mA mA mA A A pF pF pF
ILI ILO CIN CO CCLK
0 VIN VCC 0.45 VO VCC fC = 1 MHz (6) fC = 1 MHz (6) fC = 1 MHz (6)
NOTES: 1. For three-state outputs, this parameter is measured at: Address/Data ............................................................................................................................................................................................. 4.0 mA Controls ...................................................................................................................................................................................................... 5.0 mA 2. For open-drain outputs ................................................................................................................................................................................ 25 mA 3. This parameter is measured at: Address/Data ........................................................................................................................................................................................... -1.0 mA Controls .................................................................................................................................................................................................... -0.9 mA ALE .......................................................................................................................................................................................................... -5.0 mA 4. Not measured on open-drain outputs. 5. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions in Figures 12 and 13. Figure 7, Figure 8 and Figure 9 indicate typical values. 6. Input, output and clock capacitance are not tested.
15
80960KB
2.8.
AC Specifications
This section describes the AC specifications for the 80960KB pins. All input and output timings are specified relative to the 1.5 V level of the rising edge of CLK2. For output timings the specifications refer to the time it takes the signal to reach 1.5 V.
For input timings the specifications refer to the time at which the signal reaches (for input setup) or leaves (for hold time) the TTL levels of LOW (0.8 V) or HIGH (2.0 V). All AC testing should be done with input voltages of 0.4 V and 2.4 V, except for the clock (CLK2), which should be tested with input voltages of 0.45 V and 0.55 VCC.
EDGE
A
B
C
D
A
B
C
CLK2
0.8V
1.5V
1.5V
1.5V
1.5V
OUTPUTS: LAD 31:0 ADS W/R, DEN BE3:0 HLDA CACHE LOCK, INTA
T6
1.5V
T9
VALID OUTPUT 1.5V
T8
T8 T13
1.5V 1.5V
T14
ALE
T7 T6
DT/R
1.5V VALID OUTPUT
T9
1.5V
T10
INPUTS: LAD31:0 BADAC IAC/INT0, INT1 INT2/INTR, INT3 HOLD LOCK READY
2.0V 0.8V
T11
2.0V 0.8V
T12
2.0V 0.8V
T11
2.0V 0.8V
VALID INPUT
Figure 14. Drive Levels and Timing Relationships for 80960KB Signals
16
80960KB
2.8.1.
AC Specification Tables Table 7. 80960KB AC Characteristics (16 MHz)
Symbol Input Clock T1 T2 T3 T4 T5
Parameter
Min
Max
Units
Notes
Processor Clock Period (CLK2) Processor Clock Low Time (CLK2) Processor Clock High Time (CLK2) Processor Clock Fall Time (CLK2) Processor Clock Rise Time (CLK2)
31.25 8 8
125
ns ns ns
VIN = 1.5V VIL = 10% Point = 1.2V VIH = 90% Point = 0.1V + 0.5 VCC VIN = 90% Point to 10% Point (1) VIN = 10% Point to 90% Point (1)
10 10
ns ns
Synchronous Outputs T6 T6H T7 T8 T9 T9H Output Valid Delay HLDA Output Valid Delay ALE Width ALE Output Valid Delay Output Float Delay HLDA Output Float Delay 2 4 15 2 2 4 18 20 20 25 28 ns ns ns ns ns ns (2) (2)
Synchronous Inputs T10 T11 T11H T12 T13 T14 T15 T16 T17
NOTES: 1. Clock rise and fall times are not tested. 2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it should not be longer than the valid delay. 3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0 , INT1 , INT2/INTR and INT3 may be synchronous or asynchronous.
Input Setup 1 Input Hold HOLD Input Hold Input Setup 2 Setup to ALE Inactive Hold after ALE Inactive Reset Hold Reset Setup Reset Width
3 5 4 8 10 8 3 5 1281
ns ns ns ns ns ns ns ns ns
(3) (3) (3) (3)
(3) (3) 41 CLK2 Periods Minimum
17
80960KB
Table 8. 80960KB AC Characteristics (20 MHz) Symbol Input Clock T1 T2 T3 T4 T5 Processor Clock Period (CLK2) Processor Clock Low Time (CLK2) Processor Clock High Time (CLK2) Processor Clock Fall Time (CLK2) Processor Clock Rise Time (CLK2) 25 6 6 10 10 125 ns ns ns ns ns VIN = 1.5V VIL = 10% Point = 1.2V VIH = 90% Point = 0.1V + 0.5 VCC VIN = 90% Point to 10% Point (1) VIN = 10% Point to 90% Point (1) Parameter Min Max Units Notes
Synchronous Outputs T6 T6H T7 T8 T9 T9H Output Valid Delay HLDA Output Valid Delay ALE Width ALE Output Valid Delay Output Float Delay HLDA Output Float Delay 2 4 12 2 2 4 18 20 20 20 23 ns ns ns ns ns ns (2) (2)
Synchronous Inputs T10 T11 T11H T12 T13 T14 T15 T16 T17
NOTES: 1. Clock rise and fall times are not tested. 2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it should not be longer than the valid delay. 3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0 , INT1 , INT2/INTR and INT3 may be synchronous or asynchronous.
Input Setup 1 Input Hold HOLD Input Hold Input Setup 2 Setup to ALE Inactive Hold after ALE Inactive Reset Hold Reset Setup Reset Width
3 5 4 7 10 8 3 5 1025
ns ns ns ns ns ns ns ns ns
(3) (3) (3) (3)
41 CLK2 Periods Minimum
18
80960KB
Table 9. 80960KB AC Characteristics (25 MHz) Symbol Input Clock T1 T2 T3 T4 T5 Processor Clock Period (CLK2) Processor Clock Low Time (CLK2) Processor Clock High Time (CLK2) Processor Clock Fall Time (CLK2) Processor Clock Rise Time (CLK2) 20 5 5 10 10 125 ns ns ns ns ns VIN = 1.5V VIL = 10% Point = 1.2V VIH = 90% Point = 0.1V + 0.5 VCC VIN = 90% Point to 10% Point (1) VIN = 10% Point to 90% Point (1) Parameter Min Max Units Notes
Synchronous Outputs T6 T6H T7 T8 T9 T9H Output Valid Delay HLDA Output Valid Delay ALE Width ALE Output Valid Delay Output Float Delay HLDA Output Float Delay 2 4 12 2 2 4 18 18 20 18 23 ns ns ns ns ns ns (2) (2)
Synchronous Inputs T10 T11 T11H T12 T13 T14 T15 T16 T17
NOTES: 1. Clock rise and fall times are not tested. 2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it should not be longer than the valid delay. 3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0 , INT1 , INT2/INTR and INT3 may be synchronous or asynchronous.
Input Setup 1 Input Hold HOLD Input Hold Input Setup 2 Setup to ALE Inactive Hold after ALE Inactive Reset Hold Reset Setup Reset Width
3 5 4 7 8 8 3 5 820
ns ns ns ns ns ns ns ns ns
(3) (3)
41 CLK2 Periods Minimum
19
80960KB
T1 T3
HIGH LEVEL (MIN) 0.55VCC
90%
1.5 V
LOW LEVEL (MAX) 0.8V
10% T5 T4 T2
Figure 15. Processor Clock Pulse (CLK2)
CLK2
CLK
RESET
... ... ...
T17
FIRST ABC
D
A
T15 T16
OUTPUTS
...
T15 = RESET HOLD T16 = RESET SETUP T17 = RESET WIDTH
INIT PARAMETERS (BADAC, INT0/IAC) MUST BE SET UP 8 CLOCKS PRIOR TO THIS CLK2 EDGE INIT PARAMETERS MUST BE HELD BEYOND THIS CLK2 EDGE Figure 16. RESET Signal Timing
20
80960KB
3.0 3.1.
MECHANICAL DATA Packaging
3.1.1.
Pin Assignment
The 80960KB is available in two package types: * 132-lead ceramic pin-grid array (PGA). Pins are arranged 0.100 inch (2.54 mm) center-to-center, in a 14 by 14 matrix, three rows around (see Figure 17). * 132-lead plastic quad flat pack (PQFP). This package uses fine-pitch gull wing leads arranged in a single row along the package perimeter with 0.025 inch (0.64 mm) spacing (see Figure 20). Dimensions for both package types are given in the Intel Packaging handbook (Order #240800).
The PGA and PQFP have different pin assignments. Figure 18 shows the view from the PGA bottom (pins facing up) and Figure 19 shows a view from the PGA top (pins facing down). Figure 20 shows the PQFP package; Figure 21 shows the PQFP pinout with signal names. Notice that the pins are numbered in order from 1 to 132 around the package perimeter. Table 10 and Table 11 list the function of each PGA pin; Table 12 and Table 13 list the function of each PQFP pin.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 ABCD E FGH J K LMNP
Figure 17. 132-Lead Pin-Grid Array (PGA) Package
21
80960KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P VCC N VSS M N.C. L DEN K BE3 J DT/R H W/R G LAD30 READY BE1 F LAD29 LAD31 CACHE E LAD28 LAD26 LAD27 D ALE C HOLD LAD25 BADAC VCC VSS LAD20 LAD13 LAD8 LAD3 VCC B LAD23 LAD24 LAD22 LAD21 LAD18 LAD15 LAD12 LAD10 LAD6 LAD2 CLK2 LAD0 RESET VSS A VCC VSS LAD19 LAD17 LAD16 LAD14 LAD11 LAD9 LAD7 LAD5 LAD4 LAD1 INT2 VCC VSS INT3 INT1 INT0 ADS HLDA VCC N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. BE0 LOCK N.C. N.C. N.C. BE2 VSS N.C. N.C. N.C. FAIL VSS VCC N.C. N.C. N.C. VCC VSS N.C. N.C. N.C. VSS VSS VCC N.C. N.C. N.C. N.C. VSS VCC N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VCC
P
N M L K J H G F E D C B A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 18. 80960KB PGA Pinout--View from Bottom (Pins Facing Up)
22
80960KB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P VCC N N.C. M N.C. L N.C. K J N.C. H N.C. G N.C. F N.C. E N.C. VSS D N.C. C INT0 B VSS RESET LAD0 CLK2 LAD2 LAD6 LAD10 LAD12 LAD15 LAD18 LAD21 LAD22 LAD24 LAD23 A VCC INT2 LAD1 LAD4 LAD5 LAD7 LAD9 LAD11 LAD14 LAD16 LAD17 LAD19 VSS VCC INT1 INT3 VSS VCC LAD3 LAD 8 LAD13 LAD20 VSS VCC BADAC LAD25 HOLD N.C. VCC HLDA ADS ALE N.C. LAD27 LAD26 LAD28 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VCC VSS VSS N.C. FAIL BE2 DEN N.C. N.C. VCC VSS N.C. N.C. N.C. N.C. VCC VSS VSS VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VCC VSS
P
N M L K
A80960KB-25
N.C. VCC
BE3 J DT/R H W/R G
XXXXXXXX XXXXXX XXXXXX
LOCK BE0
BE1 READY LAD30 F CACHE LAD31 LAD29 E D C B A
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 19. 80960KB PGA Pinout--View from Top (Pins Facing Down)
Figure 20. 80960KB 132-Lead Plastic Quad Flat-Pack (PQFP) Package
23
80960KB
VSS NC NC NC NC NC RESET VCC CLK2 VSS NC INT3/INTA INT2/INTR INT1 IAC/INT0 VSS VCC VCC NC VSS VSS NC NC NC NC VCC VSS NC VCC VCC
LAD0 LAD1 LAD2 VSS LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 VSS LAD13 LAD14 LAD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 VSS LAD23 LAD24 LAD25 BADAC HOLD NC ADS
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
1
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
NC VSS VSS
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
NC NC NC NC NC NC NC NC NC VSS VCC VCC NC VSS VSS NC NC NC NC NC NC NC NC NC VSS VCC NC NC NC NC VCC VCC NC
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
HLDA ALE LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 VSS CACHE W/R READY DT/R BE0 BE1 BE2 BE3 FAILURE VSS LOCK DEN VSS VSS NC NC VSS VSS NC VCC VCC
NG80960KB-25
XXXXXXXX XXXXXX XXXXXX
Figure 21. PQFP Pinout - View From Top
24
NC VSS VSS
80960KB
3.2.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5
NOTE:
Pinout
Table 10. 80960KB PGA Pinout -- In Pin Order Signal VCC VSS LAD19 LAD17 LAD16 LAD14 LAD11 LAD9 LAD7 LAD5 LAD4 LAD1 INT2/INTR VCC LAD23 LAD24 LAD22 LAD21 LAD18 LAD15 LAD12 LAD10 LAD6 LAD2 CLK2 LAD0 RESET VSS HOLD LAD25 BADAC VCC VSS Pin C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D12 D13 D14 E1 E2 E3 E12 E13 E14 F1 F2 F3 F12 F13 F14 G1 G2 G3 G12 G13 G14 Signal LAD 20 LAD 13 LAD 8 LAD 3 VCC VSS INT3/INTA INT1 IAC/INT0 ALE ADS HLDA VCC N.C. N.C. LAD 28 LAD 26 LAD 27 N.C. VSS N.C. LAD 29 LAD 31 CACHE N.C. N.C. N.C. LAD 30 READY BE1 N.C. N.C. N.C. Pin H1 H2 H3 H12 H13 H14 J1 J2 J3 J12 J13 J14 K1 K2 K3 K12 K13 K14 L1 L2 L3 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 Signal W/R BE0 LOCK N.C. N.C. N.C. DT/R BE2 VSS N.C. N.C. N.C. BE3 FAILURE VSS VCC N.C. N.C. DEN N.C. VCC VSS N.C. N.C. N.C. VCC VSS VSS VCC N.C. N.C. N.C. N.C. Pin M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 VSS VCC N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VCC Signal
Do not connect any external logic to any pins marked N.C.
25
80960KB
Table 11. 80960KB PGA Pinout -- In Signal Order Signal ADS ALE BADAC BE 0 BE 1 BE 2 BE 3 CACHE CLK2 DEN DT/R FAILURE HLDA HOLD IAC/INT0 INT1 INT2/INTR INT3/INTA LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14
NOTE:
Pin D2 D1 C3 H2 G3 J2 K1 F3 B11 L1 J1 K2 D3 C1 C14 C13 A13 C12 B12 A12 B10 C9 A11 A10 B9 A9 C8 A8 B8 A7 B7 C7 A6
Signal LAD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 LOCK N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
Pin B6 A5 A4 B5 A3 C6 B4 B3 B1 B2 C2 E2 E3 E1 F1 G1 F2 H3 D13 D14 E12 E14 F12 F13 F14 G12 G13 G14 H12 H13 H14 J12 J13
Signal N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
Pin J14 K13 K14 L13 L14 M1 M6 M7 M8 M9 M12 M13 M14 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P2 P3 P4 P5 P6 P7 P8
Signal N.C. N.C. N.C. N.C. N.C. READY RESET VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R
Pin P9 P10 P11 P12 L2 G2 B13 A1 A14 C4 C10 D12 K12 L3 M2 M5 M11 P1 P14 A2 B14 C5 C11 E11 J3 K3 L12 M3 M4 M10 N1 P13 H1
Do not connect any external logic to any pins marked N.C.
26
80960KB
Table 12. 80960KB PQFP Pinout -- In Pin Order Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
NOTE:
Signal HLDA ALE LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 VSS CACHE W/R READY DT/R BE0 BE1 BE2 BE3 FAILURE VSS LOCK DEN VSS VSS N.C. N.C. VSS VSS N.C. VCC VCC N.C. VSS VSS
Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
Signal N.C. VCC VCC N.C. N.C. N.C. N.C. VCC VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VSS N.C. VCC VCC VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
Signal VSS VSS N.C. VCC VCC N.C. VSS VCC N.C. N.C. N.C. N.C. VSS VSS N.C. VCC VCC VSS IAC/INT0 INT1 INT2/INTR INT3/INTA N.C. VSS CLK2 VCC RESET N.C. N.C. N.C. N.C. N.C. VSS
Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
Signal LAD0 LAD1 LAD2 VSS LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 VSS LAD13 LAD14 LAD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 VSS LAD23 LAD24 LAD25 BADAC HOLD N.C. ADS
Do not connect any external logic to any pins marked N.C.
27
80960KB
Table 13. 80960KB PQFP Pinout -- In Signal Order Signal ADS ALE BADAC BE 0 BE 1 BE 2 BE 3 CACHE CLK2 DEN DT/R FAILURE HLDA HOLD IAC/INT0 INT1 INT2/INTR INT3/INTA LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14
NOTE:
Pin 132 2 129 14 15 16 17 10 91 21 13 18 1 130 85 86 87 88 100 101 102 104 105 106 107 108 109 110 111 112 113 115 116
Signal LAD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 LOCK N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
Pin 117 118 119 120 121 122 123 124 126 127 128 3 4 5 6 7 8 20 24 25 28 31 34 37 38 39 40 43 44 45 46 47 48
Signal N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. READY RESET VCC VCC VCC VCC
Pin 49 50 51 54 58 59 60 61 62 63 64 65 66 69 72 75 76 77 78 81 89 94 95 96 97 98 131 12 93 29 30 35 36
Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R
Pin 41 55 56 70 71 74 82 83 92 9 19 22 23 26 27 32 33 42 52 53 57 67 68 73 79 80 84 90 99 103 114 125 11
Do not connect any external logic to any pins marked N.C.
28
80960KB
3.3.
Package Thermal Specification
The 80960KB is specified for operation when case temperature is within the range 0C to 85C (PGA) or 0C to 100C (PQFP). Measure case temperature at the top center of the package. Ambient temperature can be calculated from: TJ = TC + P*jc TA = TJ + P*ja TC = TA + P*[ja-jc] Values for ja and jc for various airflows are given in Table 12 for the PGA package and in Table 12 for the PQFP package. The PGA's ja can be reduced by adding a heatsink. For the PQFP, however, a heatsink is not generally used since the device is intended to be surface mounted.
Maximum allowable ambient temperature (TA) permitted without exceeding TC is shown by the graphs in Figures 23, 24, 25 and 26. The curves assume the maximum permitted supply current (ICC) at each speed, VCC of +5.0 V and a TCASE of +85C (PGA) or +100C (PQFP). If the 80960KB is to be used in a harsh environment where the ambient temperature may exceed the limits for the normal commercial part, consider using an extended temperature device. These components are designated by the prefix "TA" and are available at 16, 20 and 25 MHz in the ceramic PGA package. Extended operating temperature range is -40 C to +125C (case). Figure 26 shows the maximum allowable ambient temperature for the 20 MHz extended temperature TA80960KB at various airflows. The curve assumes an ICC of 420 mA, VCC of 5.0 V and a TCASE of +125C.
Table 14. 80960KB PGA Package Thermal Characteristics Thermal Resistance -- C/Watt
Airflow -- ft./min (m/sec) Parameter 0 (0) 50 (0.25) 100 (0.50) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06)
Junction-to-Case Case-to-Ambient (No Heatsink) Case-to-Ambient (Omnidirectional Heatsink) Case-to-Ambient (Unidirectional Heatsink)
NOTES: 1. 2.
2 19 16
2 18 15
2 17 14
2 15 12
2 12 9
2 10 7
2 9 J-PIN 6 JA JC J-CAP
15
14
13
11
3.
8
6
5
This table applies to 80960KB PGA plugged into socket or soldered directly to board.
J-CAP = 4C/W (approx.) J-PIN = 4C/W (inner pins) (approx.) J-PIN = 8C/W (outer pins) (approx.)
JA = JC + CA
29
80960KB
Table 15. 80960KB PQFP Package Thermal Characteristics Thermal Resistance -- C/Watt
Airflow -- ft./min (m/sec) Parameter 0 (0) 50 (0.25) 100 (0.50) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06)
Junction-to-Case Case-to-Ambient (No Heatsink)
NOTES: 1. 2.
9 22
9 19
9 18
9 16
9 11
9 9
9 8
This table applies to 80960KB PQFP soldered directly to board.
3. JL = 18C/W (approx.) JB = 18C/W (approx.)
JA = JC + CA
JC JL
JB
Th CLK2
Th
Th
CLK T12 HOLD T6H HLDA T9H T11
Figure 22. HOLD Timing
30
80960KB
90 85
TEMPERATURE (o C)
80 75 70 65 60 55 0 200
PGA with no heatsink
400
AIRFLOW (ft/min) PGA with omnidirectional heatsink
600
800
PQFP
PGA with unidirectional heatsink
Figure 23. 16 MHz Maximum Allowable Ambient Temperature
90 85 80
TEMPERATURE (o C)
75 70 65 60 55 50 0 200
PGA with no heatsink
400
AIRFLOW (ft/min) PGA with omnidirectional heatsink
600
800
PQFP
PGA with unidirectional heatsink
Figure 24. 20 MHz Maximum Allowable Ambient Temperature
31
80960KB
85 80 75 TEMPERATURE (oC) 70 65 60 55 50 45 40 0 100 200 300 400 500 600 700 800 AIRFLOW (ft/min) PQFP PGA with no heatsink PGA with omnidirectional heatsink PGA with unidirectional heatsink
Figure 25. 25 MHz Maximum Allowable Ambient Temperature
120 TEMPERATURE (oC) 115 110 105 100 95 90 0 100 200 300 400 500 600 700 800
AIRFLOW (ft/min) PGA with no heatsink PGA with omnidirectional heatsink PGA with unidirectional heatsink
Figure 26. Maximum Allowable Ambient Temperature for the Extended Temperature TA-80960KB at 20 MHz in PGA Package
32
80960KB
4.0
WAVEFORMS
Figures 27, 28, 29 and 30 show the waveforms for various transactions on the 80960KB's local bus.
Ta CLK2
Td
Tr
Ta
Td
Tr
CLK
LAD31:0
ALE ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 27. Non-Burst Read and Write Transactions Without Wait States
33
80960KB
Ta CLK2
Td
Td
Tr
Ta
Td
Td
Td
Td
Tr
CLK
LAD31:0
ALE ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 28. Burst Read and Write Transaction Without Wait States
34
80960KB
Ta CLK2
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
CLK
LAD31:0
ALE ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 29. Burst Write Transaction with 2, 1, 1, 1 Wait States
35
80960KB
Ta CLK2
Tw
Td
Td
Td
Td
Tr
Ta
Tw
Td
Tr
CLK
LAD31:0
ALE
ADS
BE3:2
BE1:0
W/R
DT/R
DEN
READY
Figure 30. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States)
36
80960KB
PREVIOUS CYCLE
INTERRUPT ACKNOWLEDGEMENT CYCLE 1
IDLE (5 BUS STATES)
INTERRUPT ACKNOWLEDGEMENT CYCLE 2
TX
TX
Ta
Td
Tr
TI
TI
TI
TI
TI
Ta
Tw
Td
Tr
CLK2
CLK
INTR
LAD31:0
ADDR
ADDR
VECTOR
ALE ADS
INTA
DT/R
DEN
LOCK
READY
NOTE: INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1. For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted. Figure 31. Interrupt Acknowledge Transaction
37
80960KB
5.0
REVISION HISTORY
No revision history was maintained in earlier revisions of this data sheet. All errata that has been identified to date is incorporated into this revision. The sections significantly changed since the previous revision are: Section Table 4. 80960KB Pin Description: L-Bus Signals (pg. 8) 2.3. Connection Recommendations (pg. 11) Last Rev. -005 Description LOCK pin description rewritten for clarity.
-005
Changed suggested open-drain termination networks to reflect more realistic operating conditions with reduction in DC power consumption. Added figure for typical power supply current at hot temperature to aid thermal analysis. All outputs now specified with standard 50 pF test loads to agree with actual test methodology.
Figure 9. Typical Current vs. Frequency (Hot Temp) (pg. 13) Figure 12. Test Load Circuit for Three-State Output Pins (pg. 14) Figure 13. Test Load Circuit for Open-Drain Output Pins (pg. 14) 2.7. DC Characteristics (pg. 15)
-005
-005
-005
ICC max specification reduced:
WAS: IS: AT:
375 mA 420 mA 480 mA
315 mA 360 mA 420 mA
16 MHz 20 MHz 25 MHz
Figures 7, 8, 9, 23, 24, 25 and 26 have also been changed accordingly. 2.8. AC Specifications (pg. 16) -005 25 MHz operation extended to product in PQFP package. T8 min. improved at all frequencies from 0 ns to 2 ns and T8 max. improved from 20 ns to 18 ns. T8H max improvement:
WAS: IS: AT:
31ns 26ns 24ns Functional Waveforms -005
28ns 23ns 23ns
16 MHz 20 MHz 25 MHz
Redrawn for clarity. CLK signal drawn with more likely phase relationship to CLK2. Open-drain output signals drawn to show correct inactive states. Deleted all references to 10 MHz. Intel no longer offers a 10 MHz 80960KB device.
Various
-005
38

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